Integrated circuits often include circuitry for performing logic functions as well as circuitry for providing memory. The circuitry for memory is typically arranged in certain areas of the integrated circuit and segregated from the circuitry that performs logic functions.
One drawback of this arrangement is that interconnect requirements of logic circuitry for performing certain logic functions may be very complex and utilize all of the neighboring interconnect lines and local capacity of the routing structure. Consequently, nearby logic circuitry may not be utilized due to a lack of interconnect capability, even when a high density circuit interconnect is provided on the integrated circuit.
Furthermore, integrated circuit manufacturing may use hybrid processing that combines a high density front end process and a lower density back end process. The high density front end process implements the advanced technology circuitry (e.g., logic circuitry), while the lower density back end process implements circuit interconnect using a lower cost technology. The circuit interconnect formed with the lower density back end process further exacerbates routing congestion around the logic circuitry and makes it even more difficult to fully utilize the logic circuitry due to the limited interconnect capability. As a result, there is a need for systems and methods to improve the utilization of logic circuitry and minimize interconnect limitations.